A Long Term Evolution (LTE) is an evolution of a 3rd-Generation mobile communication (3G) technology. LTE improves and enhances the air access technology of 3G. A new generation wireless networks based on orthogonal frequency division multiplexing (OFDM) and multiple-input multiple-output (MIMO) technologies can provide a peak rate of 100 Mbit/s in downlink and 50 Mbit/s in uplink under a spectral bandwidth of 20 MHZ, thereby improving the performance of cell edge users, increasing the cell capacity and spectrum utilization ratio and reducing the system delay. According to a technical standard 3GPP TS36.211/3GPP TS36.212 protocol file of the LTE, for the uplink and downlink traffic channels of the LTE, as shown in FIG. 1, a processing flow of a transmitting side (for a downlink traffic channel, the transmitting side is an eNodeB, and for an uplink traffic channel, the transmitting side is a user equipment CUE)) includes cyclic redundancy check (CRC) 101, code block segmentation 102, Turbo encoding 103, rate matching 104, code block cascading 105, scrambling 106, modulation 107, layer mapping 108, pre-coding 109, resource mapping 110 and OFDM symbol generation 111. As shown in FIG. 2, receiving processing flow of a receiving side (for the downlink traffic channel, the receiving side is an eNodeB, and for the uplink traffic channel, the receiving side is UE) includes reception of antenna data 201, demodulation of OFDM symbol 202, demodulation of MIMO 203, demodulation 204, descrambling 205, de-code-block decascading 206, rate dematching 207, hybrid automatic repeat request (HARQ) combination 208, decoding 209, de-CRC 210, etc.
Each code block corresponds to one rate matching process, and the input of each rate matching is the output of the Turbo encoding, i.e., parallel three branches: dk(0), dk(1) and dk(2) (k=0, . . . , K−1). As shown in FIG. 3, the rate matching process structurally includes three interleaver sub-processes for respectively processing the three branches, one bit collection sub-process for summarization and one bit selection and clipping sub-process. Three branches of data are read into respectively independent sub-block interleavers in rows, NULL elements are filled in the front of an interleaving matrix with R rows and 32 columns, and data are read out in columns exchanged in columns. Then, the three branches of interleaved data vk(0), vk(1) and vk(2) (k=0, . . . , K−1) are summarized to a bit collection module, and the first branch of data is input in sequence, and the second branch of data and the third branch of data are alternately placed. Finally, beginning from k0, the NULL elements of the data in the bit collection module are skipped, and e valid data are selected in sequence as the output of the rate matching.
Rate dematching is a reverse process of the rate matching, and as shown in FIG. 4, a traditional rate dematching method includes bit recovery, bit separation and sub-block deinterleaving. The three processes are specifically realized as follows.
Bit recovery includes:
1. the following parameters are calculated: the length of each code block, the number Nd of NULL elements added in a sub-block interleaving of the rate matching, the length Ncb of a circulating cache, positions of the NULL elements in the circulating cache, a starting address k0 of rate matching output, and the number e of physical channel bits of the code block;
2. starting from address k0, data of an input sequence are input to the circulating cache in sequence; if a current address corresponds a NULL element, 0 is written into the circulating cache, otherwise, input data are written into the circulating cache; and when the address is increased to Ncb, the address is returned to 0; and
3. according to e and Ncb, a de-repetition or de-punching process, i.e., an reverse process of bit selection and clipping of the rate matching, is performed; wherein the de-repetition is combining data repeatedly sent in bit selection and clipping, and the de-punching is recovering data removed in bit selection and clipping to 0.
The bit separation corresponds to the bit collection of the rate matching. Data that have been subjected to bit recovery are read out of the circulating cache in sequence, and separated into three sub-blocks, wherein the first R×32 data are written into a sub-block interleaver S, and the last 2R×32 data are alternately written into a sub-block de-interleaver P1 and a sub-block de-interleaver P2, and R is the number of rows of an interleaving matrix.
In sub-block deinterleaving, data of three sub-blocks are respectively input in columns, switched in columns, and then output in rows, and the NULL elements added in sub-block interleaving are deleted when data are output.
Rate dematching methods for LTE in an existing technology have problems of complex processing, huge hardware resource consumption and long processing time.
This section provides background information related to the present disclosure which is not necessarily prior art.
This section provides a summary of various of implementations or examples of the technology described in the disclosure, and is not a comprehensive disclosure of the full scope or all features of the disclosed technology.